For low-power circuit applications, it may be desirable to reduce transistor off-state leakage current. One contributor to off-state leakage current is gate-induced drain leakage (GIDL) current, which is caused by band-to-band tunneling in the drain region underneath the gate. When the potential difference between the gate and drain is relatively large, the energy bands may bend near the interface between the substrate and the gate dielectric to allow valence band electrons to tunnel into the conduction band. GIDL current may also affect the thickness of the gate oxide layer because the voltage required to cause this leakage current due to band-to-band tunneling decreases with decreasing gate oxide thickness. GIDL current may also be an important consideration in the design of dynamic random access memory (DRAM) devices as it may degrade data retention time in such devices:
FIG. 1 is a block diagram of a conventional semiconductor memory device 10 that includes a control circuit 20, address buffer 30, row decoders 40, memory cell array 50, sense amplifiers 60, data control circuit 70, and column decoders 80, which are configured as shown. The control circuit 20 is used to control operations of the address buffer 30 and the row decoders 40 responsive to one or more control signals. The address buffer 30 receives an address A0-An and divides the address into a row address and a column address; which are respectively used to drive the row decoders 40 and column decoders 80. The output of the row decoders 40 is used to select particular word lines of the memory cell array 50. The output of the column decoders 80 is used to select particular bits of words stored in the memory cell array 50 via the sense amplifiers 60 and the data control circuit 70. The data control circuit 70 may, for example, output data DQ0-DQ7 corresponding to eight bits from a selected word.
FIG. 2 illustrates a conventional word line driver circuit that may be used to select word lines 50 of FIG. 1. The word line driver circuit includes a PXI generator circuit 100 that generates PXI signals responsive to a control signal ACTIVE and the two least significant bits of a decoded row address. The memory cell array 50 may include multiple memory cell array sub-blocks 50a, 50b, etc. Accordingly, the word line driver circuit includes corresponding PXID driver circuits 200 that generate PXID and PXIB driver signals responsive to the PXI signal for the respective memory cell array sub-blocks 50a, 50b, etc. Sub-block word line driver circuits 400 drive the sub-block word lines in the respective memory cell arrays 50a and 50b responsive to the PXID signal, PXIB signal, and main word line signal MWL. The MWL generating circuit 300 generates the MWL signal responsive to the ACTIVE signal and the six most significant bits of the decoded row address.
FIG. 3 is a circuit diagram of the PXI generator circuit 100, and the PXID driver circuit 200 of FIG. 2. The PXI generator circuit 100 includes a NAND gate 110 that is coupled to an inverter circuit. The inverter circuit includes two transistors: a PMOS transistor 120 and an NMOS transistor 130, which are configured as shown. The PMOS transistor 120 is coupled to a boosted voltage VPP, which may be greater than an external voltage used to power the memory device. The NMOS transistor 130 is coupled to a common reference voltage VSS. The PXID driver circuit 200 includes two inverter circuits connected in series. The first inverter circuit includes a PMOS transistor 210 and an NMOS transistor 220 that are configured as shown. The first inverter circuit outputs the signal PXIB. The second inverter circuit includes a PMOS transistor 230 and an NMOS transistor 240, which are configured as shown. The second inverter circuit generates the output signal PXID responsive to the signal PXIB.
FIG. 4 is a circuit diagram of the MWL signal generating circuit 300 and the sub-block word line driver circuit 400 of FIG. 2. The MWL signal generating circuit 300 includes PMOS transistors 310 and 340 that are connected in parallel between the boosted voltage VPP and an input terminal of a first inverter circuit. NMOS transistors 320 and 330 are connected in series between the input terminal of the first inverter circuit and a common reference voltage VSS. PMOS transistor 310 is responsive to the ACTIVE signal, NMOS transistor 320 is responsive to the six most significant bits of the decoded row address, and NMOS transistor 300 is responsive to the ACTIVE signal. The first inverter circuit includes a PMOS transistor 350 and an NMOS transistor 360, which are configures as shown. The output node A of the first inverter circuit is coupled to the gate terminal of the PMOS transistor 340. The output node A is also coupled to the input of a second inverter circuit that includes PMOS transistor 370 and NMOS transistor 380, which are configured as shown. The second inverter circuit outputs the signal MWL responsive to the output of the first inverter circuit.
The sub-block word line driver circuit 400 includes an inverter circuit that includes a PMOS transistor 410 and an NMOS transistor 420, which are configured as shown and generates the sub-block word line signal SWL responsive to the main word line signal MWL. An NMOS transistor 430, which is responsive to the PXIB signal, is coupled between the output terminal of the inverter circuit and the common reference voltage VSS. As shown in FIG. 4, the source terminal, for example, of the PMOS transistor 410, is coupled to the output of the PXID driver circuit 200.
Operations of the MWL generating circuit 300 and the sub-block word line driver circuit 400 of FIGS. 2 and 4 are illustrated in the timing diagram of FIG. 5. During an active mode of operation, the ACTIVE signal is driven to the VPP level while the voltage at node A of FIG. 4 is at either VPP or 0V depending on whether a particular decoded row address bit is selected. The main word line signal MWL is the logical inverse of the signal at node A. During a standby or precharge mode of operation, however, the ACTIVE signal is driven low (0V) while the main word line signal MWL is driven to the VPP level. As shown in FIG. 3, when the ACTIVE signal is low, the PXID signal is driven low, e.g., 0V. As the boosted voltage VPP may be approximately 4.0V in some applications, the voltage differential between the gate terminal and the source terminal, for example, of the PMOS transistor 410 of FIG. 4, may be approximately 4.0V. As the gate oxide of the PMOS transistor 410 may be relatively thin, the PMOS transistor 410 may be susceptible to GIDL current when the sub-block word line driver circuit 400 is in a standby or precharge mode of operation.